MULTI-CORE AND MANY-CORE SYSTEMS FOR EMBEDDED COMPUTING - (MC)3
Recent trends in the microprocessor industry have important ramifications for the design of the next generation of embedded computing systems. By increasing number of cores, it is possible to improve the performance while keeping the power consumption unchanged. This trend has reached the deployment stage in embedded systems ranging from small ultramobile devices to large telecommunication servers. It is also expected that the number of cores in these systems rises dramatically in the near future.
Although these systems can potentially provide significant performance benefits, in practice, there are technical challenges associated with such increased integration of homogeneous (processors) and heterogeneous multiple cores. Therefore, it is necessary to understand the physical details of both software and hardware in embedded architectures, as well as their limitations and potential for future growth. This special session addresses all aspects of multi-core and many-core embedded systems design. It presents new ideas in the multi-core field such as theory and modeling, scalable and fault tolerant design approaches and frameworks, algorithms, software, tools and applications, analysis and comparison, design techniques and emerging implementations.
Authors are invited to submit high quality papers representing original work from both the academia and industry in (but not limited to) the following topics:
- Design space exploration and design methodology for embedded multi-core and many-core systems,
- Specification and Formal modeling of embedded multi-core and many-core systems,
- Multi-core/many-core embedded system design challenges,
- Parallel programming and software for embedded multi-core and many-core systems,
- Memory management,
- 3D architectures, integration and synthesis for embedded multi-core and many-core systems,
- On-chip communication architectures and networks-on-chip for embedded systems,
- Heterogeneous multi-core and many-core architectures,
- Hardware/software co-design,
- Simulation, validation and verification,
- QoS management and performance analysis,
- Multi-core and many-core cyber-physical systems,
- Programming languages and compilers,
- Thermal-, energy-, and power-aware architectures,
- Monitoring and reconfiguration,
- System prototyping,
- Test and fault tolerance,
- Industrial practices and case studies
Programme Committee:
- Gabriel Marchesan Almeida, Germany
- Jose L. Ayala, Universidad Complutense de Madrid, Spain
- Mohamed Bakhouya, University of technology of Belfort Montbeliard, France
- Jerker Bjorkqvist, Finland
- Waltenegus Dargie, Technical University of Dresden, Germany
- Peter Ellerve, Tallin University of Technology, Estonia
- Martti Forsell, VTT, Finland
- Liang Guang, Dep. of Information Technology, Turku University, Finland
- Leandro Indrusiak, University of York, UK
- Jouni Isoaho, University of Turku, Finland
- Gert Jervan, Tallinn University of Technology, Estonia
- Shashi Kumar, Sweden
- Sebastien Lafond, Abo Akademi University, Finland
- Ville Leppanen, Turun yliopisto, Finland
- Johan Lilius, bo Akademi University, Finland
- Zhonghai Lu, Royal Institute of Technology, Sweden
- Ethiopia Nigussie, University of Turku, Finland
- Jari Nurmi, Tampere University of Technology, Finland
- Dinesh Pamunuwa, UK
- Juha Plosila, University of Turku, Finland
- Tiberiu Seceleanu, ABB Corporate Research, Sweden
- Leonidas Tsiopoulos, Abo Akademi University, Finland
- Seppo Virtanen, University of Turku, Finland
- Tomi Westerlund, University of Turku, Finland
- Haoyuan Ying, Germany
- Zhiyi Yu, Fudan, China
